`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:28:28 11/08/2008
// Design Name:   Shifter
// Module Name:   C:/Users/William Lee/Documents/cs3710/shifter_tb.v
// Project Name:  CR16
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Shifter
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module shifter_tb;

	// Inputs
	reg [15:0] data_in;
	reg right;
	reg [3:0] shiftAmount;

	// Outputs
	wire [15:0] data_out;

	// Instantiate the Unit Under Test (UUT)
	Shifter uut (
		.data_in(data_in), 
		.data_out(data_out), 
		.right(right), 
		.shiftAmount(shiftAmount)
	);

	initial begin
		// Initialize Inputs
		data_in = 0;
		right = 0;
		shiftAmount = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		data_in = 16'd256;
		shiftAmount = 4'b0001;
		#20
		right = 1;
		shiftAmount = 4'b0001;
	end
      
endmodule

